The technical areas in which volatile and nonvolatile memory devices are used are innumerable. Memory devices are used in digital cameras, measurement instruments, and the like to mention only a few.
A functional block diagram of a known memory device capable of managing low pin count (LPC) and firmware hub protocols is depicted in FIG. 1. The communication protocols LPC and firmware hub may be supported by the same device because they require similar or compatible electrical characteristics. They may be used for memory devices with the same number of input/output pins (4), including a pin for a timing signal CK—PAD and a pin for a start signal LFRAME of the preamble.
In the ensuing description reference will be made to these two protocols, though the same considerations apply for protocols different from the firmware hub and the LPC protocols, provided they are applicable to memory devices of similar electrical characteristics.
The sample device shown in FIG. 1 comprises typically a standard memory core FLASH CORE having a serial communication interface LPC/FWH INTERFACE connected to four input/output pins LPC—PAD<3:0> for conveying data and addresses to a fifth pin CK—PAD for a clock signal, and to a sixth pin LFRAME for receiving a start signal of a cycle of a communication protocol. The interface generates the chip enable (CE) and write enable (WE) commands for respectively enabling the memory and for writing in the memory.
The commands relative to the various cycles of the communication protocol containing the information relating to addresses and data are input to the device through the pins connecting the device to the external bus LPC/FWH BUS. The received data are placed in parallel by the interface circuit for conveying the data to the standard memory FLASH CORE through the address bus ADDR<20:0> and the data bus DBUS<15:0>.
A configuration circuit CAM SETTING generates two enabling signals FWH ENABLE and LPC ENABLE that configure the memory device for either a firmware hub or an LPC protocol. During testing on wafer (or EWS) while the device is being fabricated, the circuit CAM SETTING is configured so that the memory device may manage either a firmware hub or LPC protocol according to customer needs.
Typically, the circuit CAM SETTING comprises a nonvolatile (read only) memory cell FLASH EPROM that stores a bit whose value specifies the kind of protocol to be used. It is convenient to form memory devices according to this technique because it allows substantially the fabrication of a base memory device that is eventually configured for one of the protocols depending on the customer's need during the last phase of the fabrication process.
The two protocols, firmware hub and LPC, contemplate a different succession of cycles. During each cycle of the LPC protocol, a single bit is read, as depicted in FIG. 2.
For the first twelve clock cycles, the external host of the memory device controls an I/O system bus (not depicted in FIG. 1) connected to the bus PAD—EXT<3:0>. During these cycles the external host provides appropriate codes to the memory device for accessing the standard memory FLASH CORE.
The above mentioned twelve cycles are as follows: a preamble START—CODE that begins when the signal LFRAME assumes a low logic level; a cycle CYCLE—CODE that specifies whether a READ or a WRITE operation is to be performed; eight cycles ADD—CODE that provide the address of the memory location in which the host performs a read or write operation; and two cycles TAR—CODE that signal that the control of the system bus has been released.
After these two last cycles the standard memory FLASH CORE takes control of the system bus. Therefore, the memory FLASH CORE generates wait cycles SYNC—CODE during which it carries out internal operations. When it has finished reading, it makes the read data available through two further cycles DATA—L and DATA—H, and finally, through two more cycles TAR—CODE. The memory then releases control of the system bus to the external host.
FIG. 3 shows a succession of cycles for performing a read operation with a firmware hub protocol that contemplates the following: a preamble START—CODE signaling the beginning of the protocol cycle and specifying also whether a write or read operation is to be performed; a cycle IDSEL—CODE that identifies the standard memory that must communicate with the external system host; seven cycles ADD—CODE that provide the address of the location in which the host must perform a read or write operation; a cycle MSIZE that specifies the number of bytes to be read; and two cycles TAR—CODE with which the external host releases control of the system bus to the memory.
Finally, the memory transfers the read data and releases control of the system bus through a sequence of cycles identical to that of the LPC protocol described with reference to FIG. 2. The memory device of FIG. 1 is capable of decoding both protocols, but once the circuit CAM SETTING is configured during the test on wafer stage of fabrication, it supports only a single protocol.
In fact the FLASH memory cell contained in the circuit CAM SETTING needs to be reprogrammed to let the device support the other protocol, but this cannot be done by the customer but only by the manufacturer. It is very difficult if not impossible to use the memory devices by alternating different communication protocols, unless at each protocol change the circuit CAM SETTING is reconfigured by the manufacturer.